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1/22 xc9101 series pwm controlled step-up dc/dc controllers general description the xc9101 series are step-up multiple current and voltage feedback dc/dc controller ics. current sense, clock frequencies and amp feedback gain can all be externally regulated. a stable power supply is possible with output currents of up to 1.5a. with output voltage fixed internally, v out is selectable in 100mv increments within a 2.5v ~ 16.0v range ( 2.5%). for output voltages outside this range, we recommend the fb version, which has a 0.9v internal reference voltage. using this version, the required output voltage can be set-up using 2 external resistors. switching frequencies can also be set-up externally within a range of 100 ~ 600khz and therefore frequencies suited to your particular application can be selected. with the current sense function, peak currents (which flow through the driver transistor and the coil) can be controlled. soft-start time can be adjusted using external resistor and capacitor. during shutdown (ce pin=l), consumption current can be reduced to as little as 0.5 a (typ.) or less. applications mobile, cordless phones palm top computers, pdas portable games cameras, digital cameras note book pcs typical application circuit features stable operations via current & voltage multiple feedback unlimited options for peripheral selection current protection circuit ceramic capacitor compatible input voltage range : 2.5v ~ 20v output voltage range : 2.5v ~ 16v (fixed voltage type) : 30v + (adjustable type) oscillation frequency range : 100khz ~ 600khz output current : up to 1.5a package : msop-8a, sop-8 typical performance characteristics v out : 5.0v, fosc: 180khz etr0403_003
2/22 xc9101 series pin number msop-8a sop-8 pin name function 1 1 ext driver 2 2 isen current sense 3 3 v in power input 4 4 ce/ss ce/soft start 5 5 c lk clock input 6 6 cc/gain phase compensation 7 7 v out /fb voltage sense 8 8 vss ground designator description symbol description c : v out (fixed voltage type), soft-start externally set-up type of dc/dc controllers d : fb voltage, soft-start externally set-up integer : e.g. v out =2.3v =2, =3 fb products =0, =9 fixed output voltage a~h : voltages above 10v 10=a, 11=b, 12=c, 13=d, 14=e, 15=f, 16=h e.g. v out =13.5v =d, =5 oscillation frequency a : adjustable k : msop-8a package s : sop-8 r : embossed tape, standard feed device orientation l : embossed tape, reverse feed pin configuration pin assignment product classification ordering information xc9101 ????? the standard output voltages of the xc9101c series are 2.5v, 3.3v, and 5.0v. voltages other than those listed are semi-custom. msop-8a (top view) sop-8 (top view)
3/22 x c9101 series parameter symbol ratings units ext pin voltage v ext -0.3 v in 0.3 v isen pin voltage v isen -0.3 22 v v in pin voltage v in -0.3 22 v ce/ss pin voltage v ce -0.3 22 v c lk pin voltage v clk -0.3 v in 0.3 v cc/gain pin voltage v cc -0.3 v in 0.3 v v out /fb pin voltage v out /fb -0.3 22 v ext pin current i ext 100 ma msop-8a 150 power dissipation sop-8 pd 300 mw operating temperature range topr -40 85 storage temperature range tstg -55 125 block diagram absolute maximum ratings ta = 2 5
4/22 xc9101 series parameter symbol conditions min. typ. max. units circuits output voltage v out i out =300ma 3.218 3.300 3.382 v maximum operating voltage v inmax 20 v minimum operating voltage v inmin 2.5 v supply current 1 i dd1 v in =2.5v, v out= ce = setting output voltage 0.95v 150 255 a supply current 2 i dd2 v in =2.5v, ce=v in v out= setting output voltage 1.05v 90 176 a stand-by current istb v in =2.5v, ce=v out =v ss 0.5 2.0 a clk oscillation frequency fosc rt=10.0k ? , ct=220pf 280 330 380 khz fosc frequency line regulation v in ? fosc v in =2.5v ~ 20v 5 % fosc frequency temperature fluctuation topr ? fosc v in =2.5v topr=-40 ~ +85 5 % maximum duty cycle maxdty v out =set voltage0.95v 79 85 89 % minimum duty cycle mindty v out =set voltage1.05v 0 % current limit voltage i lim v in pin voltage i sen pin voltage 90 150 220 mv i sen current i isen v in =2.5v, i sen =2.5v 4.5 7 13 a ce "high" current i ceh ce=v in =2.5v, v out =0v -0.1 0 0.1 a ce "low" current i cel ce=0v, v in =2.5v, v out =0v -0.1 0 0.1 a ce "high" voltage v ceh clk oscillation starts, v out =0v, ce: voltage applied 0.6 v ce "low" voltage v cel clk oscillation stops, v out =0v, ce: voltage applied 0.2 v ext "high" on resistance r exth ext=v in 0.4v, ce=v in =2.5v v out =setting voltage0.95v 31 58 ext "low" on resistance r extl ext=0.4v, ce=v in =2.5v v out =setting voltage1.05 27 45 efficiency (*1) effi 88 % soft-start time t ss connect c ss and r ss , ce : 0v 2.5v 5 10 20 ms cc/gain pin output impedance r ccgain 400 k electrical characteristics xc9101c33akr unless otherwise stated, v in = 2.5v note: *1: effi = {[(output voltage) (output current)] [(input voltage) (input current)]} 100 *2: the capacity range of the capacitor used to set the external clk frequency is 150 ~ 220pf ta = 2 5
5/22 x c9101 series parameter symbol conditions min. typ. max. units circuits output voltage v out i out =300ma 4.875 5.000 5.125 v maximum operating voltage v inmax 20 v minimum operating voltage v inmin 2.5 v supply current 1 i dd1 v in =3.0v, v out =ce= setting output voltage0.95v 160 270 a supply current 2 i dd2 v in =3.0v, ce=v in v out= setting output voltage 1.05v 90 176 a stand-by current istb vin=3.0v, ce=vout=vss 0.5 2.0 a clk oscillation frequency fosc rt=10.0k ? , ct=220pf 280 330 380 khz fosc frequency line regulation v in ? fosc v in =2.5v 20v 5 % fosc frequency temperature fluctuation topr ? fosc v in =2.5v topr=-40 +85 5 % maximum duty cycle maxdty v out =setting voltage0.95v 79 85 89 % minimum duty cycle mindty v out =setting voltage1.05v 0 % current limit voltage i lim v in pin voltage i sen pin voltage 90 150 220 mv i sen current i isen v in =3.0v, i sen =3.0v 4.5 7 13 a ce "high" current i ceh ce=v in =3.0v, v out =0v -0.1 0 0.1 a ce "low" current i cel ce=0v, v in =3.0v, v out =0v -0.1 0 0.1 a ce "high" voltage v ceh clk oscillation starts, v out =0v, ce: voltage applied 0.6 v ce "low" voltage v cel clk oscillation stops, v out =0v, ce: voltage applied 0.2 v ext "high" on resistance r exth ext=v in 0.4v, ce=v in =3.0v v out =setting voltage0.95v 27 51 ext "low" on resistance r extl ext=0.4v, ce=v in =3.0v v out =setting voltage1.05v 25 37 efficiency *1 effi 87 % soft-start time t ss connect c ss and r ss , ce: 0v 3.0v 5 ms cc/gain pin output impedance r ccgain 400 k xc9101c50akr note: unless otherwise stated, v in = 3.0v. *1: effi = {[(output voltage) (output current)] [(input voltage) (input current)]} 100 *2: the capacity range of the capacitor used to set the external clk frequency is 150 ~ 220pf ta = 2 5 electrical characteristics (continued)
6/22 xc9101 series parameter symbol conditions min. typ. max. units circuits output voltage v out i out =300ma 0.8775 0.9 0.9225 v maximum operating voltage v inmax 20 v minimum operating voltage v inmin 2.5 v supply current 1 i dd1 v in =2.5v, v in =ce, fb=0.90.95v 150 255 a supply current 2 i dd2 v in =2.5v, ce=v in , v out =0.91.05v 90 176 a stand-by current istb v in =2.5v, ce=fb=v ss 0.5 2.0 a clk oscillation frequency fosc rt=10.0k ? , ct=220pf 280 330 380 khz fosc frequency line regulation v in ? fosc v in =2.5v 20v 5 % fosc frequency temperature fluctuation topr ? fosc v in =2.5v topr=-40 +85 5 % maximum duty cycle maxdty v out =0.90.95v 79 85 89 % minimum duty cycle mindty v out =0.91.05v 0 % current limiter voltage i lim v in pin voltage i sen pin voltage 90 150 220 mv i sen current i isen v in =2.5v, i sen =2.5v 4.5 7 13 a ce "high" current i ceh ce=v in =2.5v, fb=0v -0.1 0 0.1 a ce "low" current i cel ce=0v, v in =2.5v, fb=0v -0.1 0 0.1 a ce "high" voltage v ceh clk oscillation start, fb=0v, ce: voltage applied 0.6 v ce "low" voltage v cel clk oscillation stop, fb=0v, ce: voltage applied 0.2 v ext "high" on resistance r exth ext=v in 0.4v, ce=v in v out =setting voltage0.95v 31 58 ext "low" on resistance r extl ext=0.4v, ce=v in v out =setting voltage1.05v 27 45 efficiency *1 effi 88 % soft-start time t ss connect c ss and r ss , ce : 0v 2.5v 5 10 20 ms cc/gain pin output impedance r ccgain 400 k xc9101d09akr note: unless otherwise stated, v in = 2.5v external components: r fb1 =200k , r fb2 =100k , c fb =82pf *1: effi = {[(output voltage) (output current)] [(input voltage) (input current)]} 100 *2: the capacity range of the capacitor used to set the external clk frequency is 150 ~ 220pf. ta = 2 5 electrical characteristics (continued)
7/22 x c9101 series typical application circuits xc9101c33akr xc9101c50akr nmos : xp161a1355pr coil : 22 h (cr105 sumida) resistor : 20m for i sen (npr1 koa), 33k (trimmer) for clk, 100k for ss capacitors : 180pf (ceramic) for clk, 470pf (ceramic) for cc/gain, 0.1 f (ceramic) for ss,1 f (ceramic) for bypass 47 f (os)+220 f (any) for cl, 220 f (any) for c in sd : u3fwj44n (toshiba) nmos : xp161a1355pr coil : 22 h (cr105 sumida) resistor : 20m for i sen (npr1 koa), 33k (trimmer) for clk, 100k for ss capacitors : 180pf (ceramic) for clk, 470pf (ceramic) for cc/gain, 0.1 f (ceramic) for ss,1 f (ceramic) for bypass 47 f (os)+220 f (any) for cl, 220 f(any) for c in sd : u3fwj44n (toshiba)
8/22 xc9101 series xc9101d09akr nmos : xp161a11a1pr coil : 22 h (cdrh127 sumida) resistor : 10m for i sen (npr1 koa), 33k (trimmer) for clk, 150k for ss capacitors : 180pf (ceramic) for clk, 470pf (ceramic) for cc/gain, 0.1 f (ceramic) for ss, 1 f (ceramic) for bypass 47 f (os) + 220 f (any) for cl, 220 f (any) for c in sd : u5fwj44n (toshiba) v out : 16v r fb1 : 560k r fb2 : 33k c fb : 27pf v out : 20v r fb1 : 470k r fb2 : 22k c fb : 33pf typical application circuits (continued)
9/22 x c9101 series the soft start function is made available by attaching a capac itor and resistor to the ce/ss pin. the vref voltage applied to the verr amplifier is restricted by the start-up voltage of the ce/ss pin. this ensures that the verr amplifier operates with i ts two inputs in balance, thereby preventing the on-time signal from becoming stronger than necessary. consequently, soft start time needs to be set sufficiently longer than the time set to clk. the start-up time of the ce/ss pin equals the time se t for soft start (refer to the "functional settings" section for further information). the soft start function operates when the voltage at the ce/ss pin is between 0v to 1.55v. if the voltage at the ce/ss pin doesn't start from 0v but from a mid level voltage when the power is switched on, the soft start function will become ineffective and the possibilities of large rush currents and ripple voltages occuring will be increased. operational explanation step-up dc/dc converter controllers of the xc9101 series carry out pulse width modulation (pwm) according to the multiple feedback signals of the output voltage and coil current. the internal circuits consist of different blocks that operate at v in or the stabilized power (2.0 v) of the internal regulator. the fixed output voltage of the c type and the fb pin voltage (vref = 0.9 v) of type d controller have been adjusted and set by laser-trimming. with regard to clock pulses, a capacitor and resistor connected to the clk pin generate ramp waveforms whose top and bottom are 0.7v and 0.15v, respectively. the frequency can be set within a range of 100khz to 600khz externally (refer to the "functional settings" section for further information). the clock pulses are processed to generate a signal used for synchronizing internal sequence circuits. the verr amplifier is designed to monitor the output voltage. a fraction of the voltage applied to internal resistors r1, r2 i n the case of a type c controller, and the voltage at the fb pin in the case of a type d controller, are fed back and compared with the reference voltage. in response to feedback of a voltage lower than the reference voltage, the output voltage of the verr amplifier increases. the output of the verr amplifier enters the mixer via resistor (r verr ). this signal works as a pulse width control signal during pwm operations. by connecting an external capacitor and resistor through the ce/gain pin, it is possible to set the gain and frequency characteristics of verr amplifier signals (refer to the "functional settings" section for further information). the ierr amplifier monitors the coil current. the potential difference between the v in and isen pins is sampled at each switching operation. then the potential difference is amplified or held, as necessary, and input to the mixer. the ierr amplifier outputs a signal ensuring that the greater the potential difference between the v in and i sen pins, the smaller the switching current. the gain and frequency characteristics of this amplifier are fixed internally. the mixer modulates the signal sent from verr by the signal from ierr. the modulated signal enters the pwm comparator for comparison with the sawtooth pulses generated at the clk pin. if the signal is greater than the sawtooth waveforms, a signal is sent to the output circuit to turn on the external switch. the current flowing through the coil is monitored by the limiter comparator via the v in and i sen pins. the limiter comparator outputs a signal when the potential difference between the v in and i sen pins reaches about 150 mv or more. this signal is converted to a logic signal and handled as a dff reset signal for the internal limiter circuit. when a reset signal is input, a signal is output immediately at the ext pin to turn off the mos switch. when the limiter comparator sends a signal to enable data acceptance, a signal to turn on the mos switch is output at the next clock pulse. if at this time the potential difference between the v in and i sen pins is large, operation is repeated to turn off the mos switch again. dff operates in synchronization with the clock signal of the clk pin. output signal to ext pin pwm/pfm switching signal d clk q pwm/pfm switching signal clk synchronous signal limiter signal /reset
10/22 xc9101 series operational explanation ( continued ) functional settings 1. soft start ce and soft start (ss) functions are commonly assigned to the ce/ss pin. the soft start function is effective until the voltage at the ce pin reaches approximately 1.55 v rising from 0 v. soft start time is approximated by the equation below according to values of vcont, r ss , and c ss . t = - c ss r ss ln ((vcont - 1.55) / vcont) example: when c ss = 0.1 f, r ss = 470 k , and vcont = 5 v, t = -0.1 x 10 -6 470 x 10 3 ln ((5 - 1.55) / 5) = 17.44 ms . ce/ss pin vcont css ce, uvlo vref circuit to verr amplifier rss set the soft start time to a value sufficiently longer than the period of a clock pulse. > circuit example 1: n-ch open drain ce/ss pin css rss on/off signal vcont > circuit example 2: cmos logic (low supply current) ce/ss pin css rss on/off signal vcont > circuit example 3: cmos logic (low supply current), quick off ce/ss pin css rss on/off signal vcont
11/22 x c9101 series 2. oscillation frequency the oscillation frequency of the internal clock generator is approximated by the following equation according to the values of the capacitor and resistor attached to the clk pin. to stabilize the ic's operation, set the oscillation frequency within a range of 100khz to 600khz. select a value for cclk within a range of 150pf to 220pf and fix the frequency based on the value for rclk. f = 1/(-cclk rclk ln0.26) example: when cclk = 220 pf and rclk = 10 k , f = 1 / (-220 x 10 -12 10 x 10 3 ln(0.26)) = 337.43 khz. 3. gain and frequency characteristics of the verr amplifier the gain at output and frequency characteristics of the verr amplifier are adjusted by the values of the c apacitor and resistor attached to the cc/gain pin. it is generally recommended to attach a cc of 220 to 1,000pf without r gain . the greater the cc value, the more stable the phase and the slower the transient response. when using the ic with rgain connected, it should be noted that if the r gain resistance value is too high, abnormal oscillation may occur during transient response time. the size of r gain should be carefully evaluated before connection. 4. current limit the current limit value is approximated by the following equation according to resistor r sen inserted between the v in and i sen pins. double function, current fb input and current limiting, is assigned to the i sen pin. the current limiting value is approximated by the following equation according to the value for r sen . ilpeak_limit = 0.15/rsen example: when r sen = 100 m , ilpeak_limit = 0.15/0.1 = 1.5 a the inside error amplifier sends feedback signal when the voltage occurs at r sen resisitors because of the flow of coil current in order to phase compensate. the more the r sen value becomes larger, the more the error signal becomes bigger, and it could lead to an intermittent oscillation. please be careful if there is a problem with the application. when the regular operation, the voltage which occurs between r sen resistors because of coil peak should be set lower than the current limit voltage of 90mv (min.). for more details, please refer the notes on the external components. operational explanation (continued) functional settings (continued) clk pin rclk clk generator cclk verr cc/gain pin rgain cc v out /fb vref rverr rsen v in pin isen pin limiter signal comparator with 150 v offset
12/22 xc9101 series 5. fb voltage and c fb with regard to the xc9101d series, the output voltage is set by attaching externally divided resistors. the output voltage is determined by the equation shown below according to the values of r fb1 and r fb2 . in general, the sum of r fb1 and r fb2 should be 1 m or less. v out = 0.9 (r fb1 + r fb2 )/ r fb2 the value of c fb (phase compensation capacitor) is approximated by the following equation according to the values of r fb1 and fzfb. the value of fzfb should be 10 khz, as a general rule. c fb = 1/(2 r fb1 fzfb) example: when r fb1 = 455 k and r fb2 = 100 k : v out = 0.9 (455 k 100 k)/100 k = 4.995 v : c fb = 1/(2 455 k 10 k) = 34.98 pf notes on use application notes to 1 k according to the load and hfe of the transistor. use a ceramic capacitor for c b , complying with c b < 1/(2 r b fosc 0.7) , as a rule. 4. although the c_clk connection capacitance range is from 150 ~ 220pf, the most suitable value for maximum stability is around 180pf. operational explanation (continued) functional settings (continued) fb pin rfb1 rfb2 verr amplifier 0.9v cfb output voltage verr v in ext pin rb cb
13/22 x c9101 series instruction on pattern layout in order to stablize v dd 's voltage level, we recommend that a by-pass capacitor (c dd ) be connected as close as possible to the v in & v ss pins. in order to stablize the gnd voltage level which can fluctuate as a result of switching, we suggest that c_clk's, r_clk's & c_gain's gnd be separated from power gnd and connected as close as possible to the v ss pin (by-pass capacitor, c dd ). please use a multi layer board and check the wiring carefully. < xc9101d series pattern layout examples> 2 layer evaluation board notes on use ( continued ) power gnd ic gnd v dd line through hole rfb1 rfb2 cfb cl c_gain r_clk c_clk cdd l n-mos rsen sd v in c in c_ss r_ss 1 2 3 4 through hole 5 6 7 8 r_clk, c_clk, c_gain, rfb2 gnd 1 2 3 4 5 6 7 8 5 6 7 8 5 6 7 8
14/22 xc9101 series 1 layer evaluation board notes 1. ensure that the absolute maximum ratings of the external components and the xc9101 dc/dc ic itself are not exceeded. 2. we recommend that sufficient counter measures are put in pl ace to eliminate the heat that may be generated by the external n-ch mosfet as a result of switching losses. 3. try to use a n-ch mosfet with as small a gate capacitance as possible in order to avoid overly large output spike voltages that may occur (such spikes occur in proportion to gate c apacitance). 4. the performance of the xc9101 dc/dc converter is greatly influenced by not only its own characteristics, but also by those o f the external components it is used with. we recommend that you refer to the specifications of each component to be used and take sufficient care when selecting components. 5. wire external components as close to the ic as possible and use thick, short connecting wires to reduce wiring impedance. in particular, minimize the distance between the by-pass capacitor and the ic. 6. make sure that the gnd wiring is as strong as possible as va riations in ground potential caused by ground current at the tim e of switching may result in unstable operation of the ic. spec ifically, strengthen the ground wiring in the proximity of the v ss pin. notes on use ( continued ) instruction on pattern layout (continued) power gnd ic gnd v dd line rfb1 cl rfb2 cfb cdd l n-mos 1 2 3 4 5 6 7 8 sd v in c in c_ss r_ss rsen c_gain c_clk r_clk 5 6 7 8
15/22 x c9101 series test circuits 22 h 100m nmos sd 1 f 0.1 f 220 f r_ss clk 5 1 ext 2 isen 3 v in 4 ce/ss v out 7 gain 6 vss 8 10k 220pf 470pf 20 f rl v xc9101c33a r_ss 104k c-ss 0.1 f xc9101c50a r_ss 138k c-ss 0.1 f ? circuit (v out type) rl v 20 f 470pf rfb2 220pf 10k cfb rfb1 clk 5 1 ext 2 isen 3 v in 4 ce/ss fb 7 gain 6 vss 8 nmos sd 22 h 100m r_ss 220 f 0.1 f 1 f ? circuit (fb type) a 10k 220pf clk 5 1 ext 2 isen 3 v in 4 ce/ss gain 6 vss 8 0.1 f v out /fb 7 ? circuit clk 5 1 ext 2 isen 3 v in 4 ce/ss gain 6 vss 8 v out /fb 7 10k 220pf 0.1 f ? circuit osc clk 5 1 ext 2 isen 3 v in 4 ce/ss gain 6 vss 8 v out /fb 7 osc 10k 220pf 0.1 f ? circuit clk 5 1 ext 2 isen 3 v in 4 ce/ss gain 6 vss 8 v out /fb 7 10k 220pf 0.1 f a v v ? circuit clk 5 1 ext 2 isen 3 v in 4 ce/ss gain 6 vss 8 v out /fb 7 10k 0.1 f v a 220pf ? circuit clk 5 1 ext 2 isen 3 v in 4 ce/ss gain 6 vss 8 v out /fb 7 0.1 f 1m v ? circuit
16/22 xc9101 series typical performance characteristics xc9101d09akr (1) output voltage vs. output current
17/22 x c9101 series (2) efficiency vs. output current typical performance characteristics ( continued ) xc9101d09akr v v
18/22 xc9101 series (3) ripple voltage vs. output current typical performance characteristics ( continued ) xc9101d09akr note : if the difference between the input and output voltage is large or small, switching on/off time will be shortened. as such, the external components used and their values (inductance value of the coil, resistor connected to clk, capacitor etc. ) may have a critical influence on the actual operation of the ic.
19/22 x c9101 series packaging information msop-8a sop-8
20/22 xc9101 series mark product series 4 xc9101 xxxakx mark type product series c v out , ce pin xc9101cxxakx d fb, ce pin xc9101d09akx mark voltage (v) product series 2 2.x xc9101c2xakx 3 3.x xc9101c3xakx 4 4.x xc9101c4xakx 5 5.x xc9101c5xakx 6 6.x xc9101c6xakx 7 7.x xc9101c7xakx 8 8.x xc9101c8xakx 9 9.x xc9101c9xakx 0 fb products xc9101d09akx a 10.x xc9101caxakx b 11.x xc9101cbxakx c 12.x xc9101ccxakx d 13.x xc9101cdxakx e 14.x xc9101cexakx f 15.x xc9101cfxakx h 16.x xc9101chxakx mark voltage (v) product series 0 x.0 xc9101cx0akx 3 x.3 xc9101c3xakx 9 fb products xc9101d09akx mark type product series a adjustable frequency xc9101 xxxakx marking rule msop-8a represents product series represents type of dc/dc controller represents integral number of output voltage, or fb type represents decimal number of output voltage, fb products (ex.) represents control type of oscillation frequency msop-8a (top view) represents production lot number 0 to 9, a to z repeated (g, i, j, o, q, w excepted). note: no character inversion used.
21/22 x c9101 series mark product series 0 1 xc9101xxxasx mark type product series c vout, ce pin xc9101cxxakx d fb, ce pin xc9101d09akx mark voltage (v) product series mark voltage (v) product series 2 2.x xc9101c2xakx a 10.x xc9101caxakx 3 3.x xc9101c3xakx b 11.x xc9101cbxakx 4 4.x xc9101c4xakx c 12.x xc9101ccxakx 5 5.x xc9101c5xakx d 13.x xc9101cdxakx 6 6.x xc9101c6xakx e 14.x xc9101cexakx 7 7.x xc9101c7xakx f 15.x xc9101cfxakx 8 8.x xc9101c8xakx h 16.x xc9101chxakx 9 9.x xc9101c9xakx 0 fb products xc9101c09akx mark voltage (v) product series 0 x.0 xc9101cx0akx 3 x.3 xc9101c3xakx 9 fb products xc9101d09akx mark type product series a variable by external c and r xc9101 xxxakx mark year 0 2000 6 2006 mark production lot number 0 3 03 0 a 1a marking rule (continued) sop-8 ? represents product series represents type of dc/dc controller represents integral number of output voltage, or fb type represents decimal number of output voltage, fb type (ex.) represents control type of oscillation frequency represents the last digit of production year represents production lot number (ex.) 0 to 9, a to z repeated (g, i, j, o, q, w excepted). note: no character inversion used. sop-8 (top view)
22/22 xc9101 series 1. the products and product specifications contained herein are subject to change without notice to improve performance characteristics. consult us, or our representatives before use, to confirm that the information in this catalog is up to date. 2. we assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this catalog. 3. please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this catalog. 4. the products in this catalog are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. atomic energy; aerospace; transport; combustion and associated safety equipment thereof.) 5. please use the products listed in this catalog within the specified ranges. should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. we assume no responsibility for damage or loss due to abnormal use. 7. all rights reserved. no part of this catalog may be copied or reproduced without the prior permission of torex semiconductor ltd.

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